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pseudo differential input, 1 msps, 10-/12-bit adcs in an 8-lead sot-23 ad7441/ad7451 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2003C2007 analog devices, inc. all rights reserved. features fast throughput rate: 1 msps specified for v dd of 2.7 v to 5.25 v low power at maximum throughput rate: 4 mw maximum at 1 msps with v dd = 3 v 9.25 mw maximum at 1 msps with v dd = 5 v pseudo differential analog input wide input bandwidth: 70 db sinad at 100 khz input frequency flexible power/serial clock speed management no pipeline delays high speed serial interface: spi?-/qspi?-/microwire?-/dsp-compatible power-down mode: 1 a maximum 8-lead sot-23 and msop packages applications transducer interface battery-powered systems data acquisition systems portable instrumentation functional block diagram v ref t/h control logic 12-bit successive approximation adc gnd sclk sdata cs v dd ad7441/ad7451 v in+ v in? 03153-001 figure 1. general description the ad7441/ad7451 1 are, respectively, 10-/12-bit high speed, low power, single-supply, successive approximation (sar), analog-to-digital converters (adcs) that feature a pseudo differential analog input. these parts operate from a single 2.7 v to 5.25 v power supply and achieve very low power dissipation at high throughput rates of up to 1 msps. the ad7441/ad7451 contain a low noise, wide bandwidth, differential track-and-hold (t/h) amplifier that handles input frequencies up to 3.5 mhz. the reference voltage for these devices is applied externally to the v ref pin and can range from 100 mv to v dd , depending on the power supply and what suits the application. the conversion process and data acquisition are controlled using cs and the serial clock, allowing the device to interface with microprocessors or dsps. the input signals are sampled on the falling edge of cs when the conversion is initiated. the sar architecture of these parts ensures that there are no pipeline delays. 1 protected by u.s. patent number 6,681,332. product highlights 1. operation with 2.7 v to 5.25 v power supplies. 2. high throughput with low power consumption. with a 3 v supply, the ad7441/ad7451 offer 4 mw maxi- mum power consumption for a 1 msps throughput rate. 3. pseudo differential analog input. 4. flexible power/serial clock speed management. the conversion rate is determined by the serial clock, allowing the power to be reduced as the conversion time is reduced through the serial clock speed increase. these parts also feature a shutdown mode to maximize power efficiency at lower throughput rates. 5. variable voltage reference input. 6. no pipeline delays. 7. accurate control of sampling instant via cs input and once-off conversion control. 8. enob > 10 bits typically with 500 mv reference.
ad7441/ad7451 rev. c | page 2 of 24 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 timing specifications .................................................................. 7 timing diagrams.......................................................................... 7 absolute maximum ratings............................................................ 8 esd caution.................................................................................. 8 pin configurations and function descriptions ........................... 9 typical performance characteristics ........................................... 10 terminology .................................................................................... 12 theory of operation ...................................................................... 13 circuit information.................................................................... 13 converter operation.................................................................. 13 adc transfer function............................................................. 13 typical connection diagram ................................................... 14 analog input ............................................................................... 14 analog input structure.............................................................. 14 digital inputs .............................................................................. 15 reference ..................................................................................... 15 serial interface ............................................................................ 16 modes of operation ....................................................................... 18 normal mode.............................................................................. 18 power-down mode .................................................................... 18 power vs. throughput rate....................................................... 20 microprocessor and dsp interfacing ...................................... 20 grounding and layout hints.................................................... 22 evaluating performance ............................................................ 22 outline dimensions ....................................................................... 23 ordering guide .......................................................................... 24 revision history 3 /07rev. b to rev. c changes to table 5.................................................................................9 updated layout....................................................................................12 changes to terminology section.......................................................12 updated outline dimensions ............................................................23 changes to ordering guide ...............................................................24 2/05rev. a to rev. b changes to ordering guide ...............................................................24 2/04rev. 0 to rev. a updated format.....................................................................universal changes to general description ....................................................... 1 changes to table 1 footnotes ............................................................ 4 changes to table 2 footnotes ............................................................ 6 changes to table 3 footnotes ............................................................ 7 changes to table 5 .............................................................................. 9 updated figures 7, 8, and 9.............................................................. 13 changes to figure 23......................................................................... 16 changes to reference section.......................................................... 17 9/03revision 0: initial version
ad7441/ad7451 rev. c | page 3 of 24 specifications v dd = 2.7 v to 5.25 v; f sclk = 18 mhz; f s = 1 msps; v ref = 2.5 v; t a = t min to t max , unless otherwise noted. temperature ranges for a, b versions: ?40c to +85c. table 1. ad7451 parameter test conditions/comments a version b version unit dynamic performance f in = 100 khz signal-to-noise ratio (snr) 1 v dd = 2.7 v to 5.25 v 70 70 db min signal-to-(noise + distortion) (sinad) 1 v dd = 2.7 v to 3.6 v 69 69 db min v dd = 4.75 v to 5.25 v 70 70 db min total harmonic distortion (thd) 1 v dd = 2.7 v to 3.6 v; ?78 db typ ?73 ?73 db max v dd = 4.75 v to 5.25 v; ?80 db typ ?75 ?75 db max peak harmonic or spurious noise 1 v dd = 2.7 v to 3.6 v; ?80 db typ ?73 ?73 db max v dd = 4.75 v to 5.25 v; ?82 db typ ?75 ?75 db max intermodulation distortion (imd) 1 fa = 90 khz; fb = 110 khz second-order terms ?80 ?80 db typ third-order terms ?80 ?80 db typ aperture delay 1 5 5 ns typ aperture jitter 1 50 50 ps typ full-power bandwidth 1 , 2 @ ?3 db 20 20 mhz typ @ ?0.1 db 2.5 2.5 mhz typ dc accuracy resolution 12 12 bits integral nonlinearity (inl) 1 1.5 1 lsb max differential nonlinearity (dnl) 1 guaranteed no missed codes to 12 bits 0.95 0.95 lsb max offset error 1 3.5 3.5 lsb max gain error 1 3 3 lsb max analog input full-scale input span v in+ ? v inC v ref v ref v absolute input voltage v in+ v ref v ref v v inC 3 v dd = 2.7 v to 3.6 v ?0.1 to +0.4 ?0.1 to +0.4 v v dd = 4.75 v to 5.25 v ?0.1 to +1.5 ?0.1 to +1.5 v dc leakage current 1 1 a max input capacitance when in track-and-hold 30/10 30/10 pf typ reference input v ref input voltage 4 1% tolerance for specified performance 2.5 2.5 v dc leakage current 1 1 a max v ref input capacitance when in track-and-hold 10/30 10/30 pf typ logic inputs input high voltage, v inh 2.4 2.4 v min input low voltage, v inl 0.8 0.8 v max input current, i in typically 10 na, v in = 0 v or v dd 1 1 a max input capacitance, c in 5 10 10 pf max logic outputs output high voltage, v oh v dd = 4.75 v to 5.25 v; i source = 200 a 2.8 2.8 v min v dd = 2.7 v to 3.6 v; i source = 200 a 2.4 2.4 v min output low voltage, v ol i sink = 200 a 0.4 0.4 v max floating-state leakage current 1 1 a max floating-state output capacitance 5 10 10 pf max output coding straight (natural) binary straight (natural) binary
ad7441/ad7451 rev. c | page 4 of 24 test conditions/comments a version b version unit parameter conversion rate conversion time 888 ns with an 18 mhz sclk 16 16 sclk cycles track-and-hold acquisition time 1 sine wave input 250 250 ns max full-scale step input 290 290 ns max throughput rate 1 1 msps max power requirements v dd 2.7/5.25 2.7/5.25 v min/max i dd 6 , 7 normal mode (static) sclk on or off 0.5 0.5 ma typ normal mode (operational) v dd = 4.75 v to 5.25 v 1.95 1.95 ma max v dd = 2.7 v to 3.6 v 1.45 1.45 ma max full power-down mode sclk on or off 1 1 a max power dissipation normal mode (operational) v dd = 5 v; 1.55 mw typical for 100 ksps 6 9.25 9.25 mw max v dd = 3 v; 0.6 mw typical for 100 ksps 6 4 4 mw max full power-down v dd = 5 v; sclk on or off 5 5 w max v dd = 3 v; sclk on or off 3 3 w max 1 see terminology section. 2 analog inputs with slew rates exceeding 27 v/s (full-scale input sine wave > 3.5 mhz) within the acquisition time can cause t he converter to return an incorrect result. 3 a small dc input is applied to v inC to provide a pseudo ground for v in+ . 4 the ad7451 is functional with a referenc e input in the range of 100 mv to v dd . 5 guaranteed by characterization. 6 see the power vs. throughput rate section. 7 measured with a full-scale dc input.
ad7441/ad7451 rev. c | page 5 of 24 v dd = 2.7 v to 5.25 v; f sclk = 18 mhz; f s = 1 msps; v ref = 2.5 v; t a = t min to t max , unless otherwise noted. temperature range for b version: ?40c to +85c. table 2. ad7441 parameter test conditions/comments b version unit dynamic performance f in = 100 khz signal-to-(noise + distortion) (sinad) 1 61 db min total harmonic distortion (thd) 1 2.7 v to 3.6 v; ?77 db typical ?72 db max 4.75 v to 5.25 v; ?79 db typical ?73 db max peak harmonic or spurious noise 1 2.7 v to 3.6 v; ?80 db typical ?72 db max 4.75 v to 5.25 v; ?82 db typical ?74 db max intermodulation distortion (imd) 1 fa = 90 khz, fb = 110 khz second-order terms ?80 db typ third-order terms ?80 db typ aperture delay 1 5 ns typ aperture jitter 1 50 ps typ full-power bandwidth 1 , 2 @ ?3 db 20 mhz typ @ ?0.1 db 2.5 mhz typ dc accuracy resolution 10 bits integral nonlinearity (inl) 1 0.5 lsb max differential nonlinearity (dnl) 1 guaranteed no missed codes to 10 bits 0.5 lsb max offset error 1 1 lsb max gain error 1 1 lsb max analog input full-scale input span v in+ ? v inC v ref v absolute input voltage v in+ v ref v v inC 3 v dd = 2.7 v to 3.6 v ?0.1 to +0.4 v v dd = 4.75 v to 5.25 v ?0.1 to +1.5 v dc leakage current 1 a max input capacitance when in track-and-hold 30/10 pf typ reference input v ref input voltage 4 1% tolerance for specified performance 2.5 v dc leakage current 1 a max v ref input capacitance when in track-and-hold 10/30 pf typ logic inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current, i in typically 10 na, v in = 0 v or v dd 1 a max input capacitance, c in 5 10 pf max logic outputs output high voltage, v oh v dd = 4.75 v to 5.25 v; i source = 200 a 2.8 v min v dd = 2.7 v to 3.6 v; i source = 200 a 2.4 v min output low voltage, v ol i sink = 200 a 0.4 v max floating-state leakage current 1 a max floating-state output capacitance 5 10 pf max output coding straight (natural) binary
ad7441/ad7451 rev. c | page 6 of 24 test conditions/comments b version unit parameter conversion rate conversion time 888 ns with an 18 mhz sclk 16 sclk cycles track-and-hold acquisition time 1 sine wave input 250 ns max step input 290 ns max throughput rate 1 msps max power requirements v dd 2.7/5.25 v min/max i dd 6 , 7 normal mode (static) sclk on or off 0.5 ma typ normal mode (operational) v dd = 4.75 v to 5.25 v 1.95 ma max v dd = 2.7 v to 3.6 v 1.25 ma max full power-down mode sclk on or off 1 a max power dissipation normal mode (operational) v dd = 5 v; 1.55 mw typ for 100 ksps 6 9.25 mw max v dd = 3 v; 0.6 mw typ for 100 ksps 6 4 mw max full power-down v dd = 5 v; sclk on or off 5 w max v dd = 3 v; sclk on or off 3 w max 1 see the terminology section. 2 analog inputs with slew rates exceeding 27 v/s (full-scale input sine wave > 3.5 mhz) within the acquisition time can cause t he converter to return an incorrect result. 3 a small dc input is applied to v inC to provide a pseudo ground for v in+ . 4 the ad7441 is functional with a refere nce input in the range 100 mv to v dd . 5 guaranteed by characterization. 6 see the power vs. throughput rate section. 7 measured with a full-scale dc input.
ad7441/ad7451 rev. c | page 7 of 24 timing specifications 1 v dd = 2.7 v to 5.25 v; f sclk = 18 mhz; f s = 1 msps; v ref = 2.5 v; t a = t min to t max , unless otherwise noted. table 3. parameter limit at t min , t max unit description 10 khz min f sclk 2 18 mhz max 16 t sclk t sclk = 1/f sclk t convert 888 ns max 60 ns min minimum quiet time between end of a serial read and next falling edge of cs t quiet 10 ns min minimum cs pulse width t 1 10 ns min cs falling edge to sclk falling edge setup time t 2 20 ns max delay from cs falling edge until sdata three-state disabled t 3 3 t 4 40 ns max data access time after sclk falling edge t 5 0.4 t sclk ns min sclk high pulse width t 6 0.4 t sclk ns min sclk low pulse width t 7 10 ns min sclk edge to data valid hold time t 8 4 10 ns min sclk falling edge to sdata, three-state enabled 35 ns max sclk falling edge to sdata, three-state enabled t power-up 5 1 s max power-up time from full power-down 1 guaranteed by characterization. all input signals are specified with t rise = t fall = 5 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 v. see figure 2, figure 3, and the serial interface section. 2 mark/space ratio for the sc lk input is 40/60 to 60/40. 3 measured with the load circuit of figure 4 and defined as the time required for the output to cross 0.8 v or 2.4 v with v dd = 5 v and the time required for an output to cross 0.4 v or 2.0 v for v dd = 3 v. 4 t 8 is derived from the measured time taken by the data outputs to change 0.5 v when loaded with the circuit of figure 4. the meas ured number is then extrapolated back to remove the effects of charging or discharging the 25 pf capacitor. this means that the time (t 8 ) quoted in the timing characteri stics is the true bus relinquish time of the part and is in dependent of the bus loading. 5 see the power-up time section. timing diagrams t 3 t 2 t 4 t 7 t 8 t 6 t 1 t 5 t quiet t convert cs sclk sdata 4 leading zeros three-state 12345 13141516 0 0 0 0 db11 db10 db2 db1 db0 b 03153-002 figure 2. ad7451 serial interface timing diagram t 3 t 2 t 4 t 7 t 8 t 6 t 1 t 5 t quiet t convert cs sclk sdat a 4 leading zeros 2 trailing zeros three-state 12345 13141516 0 0 0 0 db9 db8 db0 0 0 b 03153-003 figure 3. ad7441 serial interface timing diagram
ad7441/ad7451 rev. c | page 8 of 24 absolute maximum ratings t a = 25c, unless otherwise noted. table 4. parameter rating v dd to gnd ?0.3 v to +7 v v in+ to gnd ?0.3 v to v dd + 0.3 v v inC to gnd ?0.3 v to v dd + 0.3 v digital input voltage to gnd ?0.3 v to +7 v digital output voltage to gnd ?0.3 v to v dd + 0.3 v v ref to gnd ?0.3 v to v dd + 0.3 v input current to any pin except supplies 1 10 ma operating temperature range commercial (a, b version) ?40c to +85c storage temperature range ?65c to +150c junction temperature 150c ja thermal impedance 205.9c/w (msop) 211.5c/w (sot-23) jc thermal impedance 43.74c/w (msop) 91.99c/w (sot-23) lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c esd 1 kv 1 transient currents of up to 100 ma do not cause scr latch-up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1.6ma i ol 200a i oh 1.6v to output pin c l 25pf 03153-004 figure 4. load circuit for digita l output timing specifications esd caution
ad7441/ad7451 rev. c | page 9 of 24 pin configurations and function descriptions v dd sclk sdata cs 8 7 6 5 v ref 1 v in+ 2 v in? 3 gnd 4 ad7441/ ad7451 top view (not to scale) 0 3153-006 figure 5. 8-lead msop pin configuration v ref v in+ v in? gnd 8 7 6 5 v dd 1 sclk 2 sdata 3 cs 4 ad7441/ ad7451 top view (not to scale) 0 3153-005 figure 6. 8-lead sot-23 pin configuration table 5. pin function descriptions pin. no. msop sot-23 mnemonic description 1 8 v ref reference input for the ad7441/ad7451. an external reference in the range of 100 mv to v dd must be applied to this input. the specified reference input is 2.5 v. this pin is decoupled to gnd with a capacitor of at least 0.1 f. 2 7 v in+ noninverting analog input. 3 6 v inC inverting input. this pin sets the ground reference point for the v in+ input. connect to ground or to a dc offset to provide a pseudo ground. 4 5 gnd analog ground. ground reference point for all circ uitry on the ad7441/ad7451. all analog input signals and any external reference signal are referred to this gnd voltage. 5 4 cs chip select. active low logic input. this input provid es the dual function of in itiating a conversion on the ad7441/ad7451 and framing the serial data transfer. 6 3 sdata serial data, logic output. the conversion result from the ad7441/ad7451 is prov ided on this output as a serial data stream. the bits are clocked out on the falling edge of the sclk input. the data stream of the ad7451 consists of four leading zeros followed by the 12 bits of conversion data that are provided msb first; the data stream of the ad7441 consists of four leading zeros, followed by the 10 bits of con- version data, followed by two trailing zeros. in both cases, the output coding is straight (natural) binary. 7 2 sclk serial clock, logic input. sclk provides the serial cl ock for accessing data from the part. this clock input is also used as the clock sour ce for the conversion process. 8 1 v dd power supply input. v dd is 2.7 v to 5.25 v. this supply is deco upled to gnd with a 0.1 f capacitor and a 10 f tantalum capacitor.
ad7441/ad7451 rev. c | page 10 of 24 typical performance characteristics t a = 25c, f s = 1 msps, f sclk = 18 mhz, v dd = 2.7 v to 5.25 v, v ref = 2.5 v, unless otherwise noted. 75 55 60 65 70 10 100 1000 frequency (khz) sinad (db) v dd = 5.25v v dd = 4.75v v dd = 3.6v v dd = 2.7v 03153-007 figure 7. sinad vs. analog input frequency for the ad7451 for various supply voltages 0 ?120 ?80 ?100 ?60 ?40 ?20 0 100 200 300 400 500 600 700 800 900 1000 supply ripple frequency (khz) psrr (db) 100mv p-p sine wave on v dd no decoupling on v dd v dd = 3v v dd = 5v 03153-008 figure 8. psrr vs. supply ripple freq uency without supply decoupling frequency (khz) snr (db) 0 100 200 ?100 ?140 500 ?20 0 ?120 ?40 ?60 ?80 8192 point fft f sample = 1msps f in = 100ksps sinad = 71db thd = ?82db sfdr = ?83db 300 400 03153-009 figure 9. ad7451 dynamic performance for v dd = 5 v dnl error (lsb) code 0.4 0 1024 2048 3072 0.2 0 ?0.2 ?0.4 ?1.0 4096 0.6 0.8 1.0 ?0.6 ?0.8 03153-010 figure 10. typical dnl for the ad7451 for v dd = 5 v inl error (lsb) code 0.4 0 1024 2048 3072 0.2 0 ?0.2 ?0.4 ?1.0 4096 0.6 0.8 1.0 ?0.6 ?0.8 03153-011 figure 11. typical inl for the ad7451 for v dd = 5 v counts codes 0 2046 2047 2048 2049 2050 2051 27 codes 24 codes 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 9949 codes 03153-012 figure 12. histogram of 10,000 conversions of a dc input for the ad7451
ad7441/ad7451 rev. c | page 11 of 24 5 change in dnl (lsb) ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 01234 4.0 v ref (v) positive dnl negative dnl 03153-013 figure 13. change in dnl vs. v ref for v dd = 5 v change in inl (lsb) ?2 ?1 0 1 2 3 4 01234 5 v ref (v) 5 positive dnl negative dnl 03153-014 figure 14. change in inl vs. v ref for v dd = 5 v effective number of bits 6 7 8 9 10 11 012345 12 v ref (v) v dd = 3v v dd = 5v 03153-015 figure 15. enob vs. v ref for v dd = 5 v and 3 v snr (db) 0 100 200 300 400 500 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 v ref (v) 8192 point fft f sample = 1msps f in = 100ksps sinad = 61.7db thd = ?81.7db sfdr = ?82db 03153-016 figure 16. ad7441 dynamic performance dnl error (lsb) 0 256 512 768 1024 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 code 0 3153-017 figure 17. typical dnl for the ad7441 inl error (lsb) 0 256 512 768 1024 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 code 0 3153-018 figure 18. typical inl for the ad7441
ad7441/ad7451 rev. c | page 12 of 24 terminology signal-to-(noise + distortion) ratio (sinad) this is the measured ratio of sinad at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process: the more levels, the smaller the quantization noise. the theoretical sinad ratio for an ideal n-bit converter with a sine wave input is given by signal-to-(noise + distortion) = ( 6.02 n + 1.76) db therefore, for 12-bit converters, the sinad is 74 db; for 10-bit converters, the sinad is 62 db. total harmonic distortion (thd) thd is the ratio of the rms sum of harmonics to the fundamental. in the ad7441/ad7451, thd is () 1 65432 v vvvvv thd 22222 log20db ++++ = where: v 1 is the rms amplitude of the fundamental. v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second to the sixth harmonics. peak harmonic or spurious noise peak harmonic (spurious noise) is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2, excluding dc) to the rms value of the fundamental. normally, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it is a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, an active device with nonlinearities creates distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, and so on. intermodulation distortion terms are those in which neither m nor n are equal to zero. for example, the second- order terms include (fa + fb) and (fa ? fb), while the third-order terms include (2fa + fb), (2fa ? fb), (fa + 2fb), and (fa ? 2fb). the ad7441/ad7451 are tested using the ccif standard where two input frequencies near the top end of the input bandwidth are used. in this case, the second-order terms are usually dis- tanced in frequency from the original sine waves while the third-order terms are usually at a frequency close to the input frequencies. as a result, the second- and third-order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels. aperture delay this is the amount of time from the leading edge of the sampling clock until the adc actually takes the sample. aperture jitter this is the sample-to-sample variation in the effective point in time at which the actual sample is taken. full power bandwidth the full power bandwidth of an adc is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 0.1 db or 3 db for a full-scale input. integral nonlinearity (inl) this is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. differential nonlinearity (dnl) this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error this is the deviation of the first code transition (000000 to 000001) from the ideal (that is, agnd + 1 lsb). gain error this is the deviation of the last code transition (111110 to 111111) from the ideal (that is, v ref ? 1 lsb) after the offset error has been adjusted out. track-and-hold acquisition time the track-and-hold acquisition time is the minimum time required for the track-and-hold amplifier to remain in track mode for its output to reach and settle to within 0.5 lsb of the applied input signal. power supply rejection ratio (psrr) the power supply rejection ratio is defined as the ratio of the power in the adc output at full-scale frequency (f) to the power of a 100 mv p-p sine wave applied to the adc v dd supply of frequency f s . the frequency of this input varies from 1 khz to 1 mhz. psrr (db) = 10log( pf/pfs ) where: pf is the power at frequency f in the adc output. pfs is the power at frequency fs in the adc output.
ad7441/ad7451 rev. c | page 13 of 24 theory of operation circuit information the ad7441/ad7451 are 10-/12-bit, high speed, low power, single-supply, successive approximation, analog-to-digital con- verters (adcs) with a pseudo differential analog input. these parts operate with a single 2.7 v to 5.25 v power supply and are capable of throughput rates up to 1 msps when supplied with an 18 mhz sclk. the ad7441/ad7451 require an external reference to be applied to the v ref pin. the ad7441/ad7451 have a sar adc, an on-chip differential track-and-hold amplifier, and a serial interface housed in either an 8-lead sot-23 or an msop package. the serial clock input accesses data from the part and provides the clock source for the sar adc. the ad7441/ad7451 feature a power-down option for reduced power consumption between conversions. the power-down feature is implemented across the standard serial interface, as described in the modes of operation section. converter operation the ad7441/ad7451 are sar adcs based around two capacitive dacs. figure 19 and figure 20 show simplified schematics of the adc in the acquisition and conversion phase, respectively. the adc is comprised of control logic, an sar, and two capacitive dacs. in figure 19 (acquisition phase), sw3 is closed, sw1 and sw2 are in position a, the comparator is held in a balanced condition, and the sampling capacitor arrays acquire the differential signal on the input. v in+ v in? a b sw1 sw3 comparator control logic capacitive dac capacitive dac c s c s v ref sw2 b a 03153-019 figure 19. adc acquisition phase when the adc starts a conversion (see figure 20 ), sw3 opens and sw1 and sw2 move to position b, causing the comparator to become unbalanced. both inputs are disconnected once the conversion begins. the control logic and the charge redistribu- tion dacs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. when the comparator is rebal- anced, the conversion is complete. the control logic generates the adc output code. the output impedances of the sources driving the v in+ and v inC pins must be matched; otherwise the two inputs have different settling times, resulting in errors. v in+ v in? a b sw1 sw3 comparator control logic capacitive dac capacitive dac c s c s v ref sw2 b a 03153-020 figure 20. adc conversion phase adc transfer function the output coding for the ad7441/ad7451 is straight (natural) binary. the designed code transitions occur at successive lsb values (1 lsb, 2 lsb, and so on). the lsb size of the ad7451 is v ref /4096, and the lsb size of the ad7441 is v ref /1024. the ideal transfer characteristic of the ad7441/ad7451 is shown in figure 21 . 000...000 0v adc code analog input 111...111 000...001 111...000 011...111 111...110 000...010 1lsb = v ref / 4096 (ad7451) 1lsb = v ref /1024 (ad7441) v ref ? 1lsb 1lsb 03153-021 figure 21. ad7441/ad7451 ideal transfer characteristic
ad7441/ad7451 rev. c | page 14 of 24 typical connection diagram figure 22 shows a typical connection diagram for the device. in this setup, the gnd pin is connected to the analog ground plane of the system. the v ref pin is connected to the ad780 , a 2.5 v decoupled reference source. the signal source is connected to the v in+ analog input via a unity gain buffer. a dc voltage is connected to the v inC pin to provide a pseudo ground for the v in+ input. the v dd pin is decoupled to agnd with a 10 f tantalum capacitor in parallel with a 0.1 f ceramic capacitor. the reference pin is decoupled to agnd with a capacitor of at least 0.1 f. the conversion result is output in a 16-bit word with four leading zeros followed by the msb of the 12-bit or 10-bit result. the 10-bit result of the ad7441 is followed by two trailing zeros. ad7441/ ad7451 0.1f 0.1f 10f v ref v dd dc input voltage v in+ sclk 2.7v to 5.25 v supply serial interface c/p sdata cs gnd v in? 2.5v ad780 v ref p-p 03153-022 figure 22. typical connection diagram analog input the ad7441/ad7451 have a pseudo differential analog input. the v in+ input is coupled to the signal source and must have an amplitude of v ref p-p to make use of the full dynamic range of the part. a dc input is applied to the v inC . the voltage applied to this input provides an offset from ground or a pseudo ground for the v in+ input. pseudo differential inputs separate the analog input signal ground from the adc ground, allowing dc common- mode voltages to be cancelled. because the adc operates from a single supply, it is necessary to level shift ground-based bipolar signals to comply with the input requirements. an op amp (for example, the ad8021 ) can be configured to rescale and level shift a ground-based (bipolar) signal so that it is compatible with the input range of the ad7441/ ad7451 (see figure 23 ). when a conversion takes place, the pseudo ground corresponds to 0, and the maximum analog input corresponds to 4096 for the ad7451 and 1024 for the ad7441. r 2.5 v 1.25v 0v +1.25v 0v ?1.25v r 3r 0.1f r ad7441/ ad7451 v in+ v in+ v in? v ref external v ref (2.5v) 0 3153-023 figure 23. op amp configuration to level shift a bipolar input signal analog input structure figure 24 shows the equivalent circuit of the analog input structure of the ad7441/ad7451. the four diodes provide esd protection for the analog inputs. care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mv. this causes these diodes to become forward-biased and start conducting into the substrate. these diodes can conduct up to 10 ma without causing irreversible damage to the part. the c1 capacitors (see figure 24 ) are typically 4 pf and can be attributed primarily to pin capaci- tance. the resistors are lumped components made up of the on resistance of the switches. the value of these resistors is typically about 100 . the c2 capacitors are the adc sampling capacitors and have a capacitance of 16 pf typically. for ac applications, removing high frequency components from the analog input signal through the use of an rc low-pass filter on the relevant analog input pins is recommended. in applica- tions where harmonic distortion and the signal-to-noise ratio are critical, it is recommended that the analog input be driven from a low impedance source. large source impedances significantly affect the ac performance of the adc, which can necessitate the use of an input buffer amplifier. the choice of the amplifier is a function of the particular application. c1 c2 r1 d d c1 c2 r1 d d v dd v dd v in+ v in? 03153-024 figure 24. equivalent analog input circuit; conversion phaseswitches open; track phaseswitches closed
ad7441/ad7451 rev. c | page 15 of 24 when no amplifier is used to drive the analog input, it is recommended that the source impedance be limited to low values. the maximum source impedance depends on the amount of total harmonic distortion that can be tolerated. the thd increases as the source impedance increases and performance degrades. figure 25 shows a graph of thd vs. analog input signal frequency for different source impedances. 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?10 ?20 10k 100k 1m input frequency (hz) thd (db) 200 ? 100 ? 62 ? 10? t a = 25c v dd = 5v 03153-025 figure 25. thd vs. analog input frequency for various source impedances figure 26 shows a graph of thd vs. analog input frequency for various supply voltages while sampling at 1 msps with an sclk of 18 mhz. in this case, the source impedance is 10 . ? 50 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 10 100 1000 input frequency (khz) thd (db) t a = 25c v dd = 2.7v v dd = 3.6v v dd = 4.75v v dd = 5.25v 03153-026 figure 26. thd vs. analog input frequency for various supply voltages digital inputs the digital inputs applied to the ad7441/ad7451 are not limited by the maximum ratings that limit the analog inputs. instead, the digital inputs applied, that is, cs and sclk, can go to 7 v and are not restricted by the v dd + 0.3 v limits as on the analog input. the main advantage of the inputs not being restricted to the v dd + 0.3 v limit is that power supply sequencing issues are avoided. if cs or sclk are applied before v dd , there is no risk of latch-up as there would be on the analog inputs if a signal greater than 0.3 v were applied prior to v dd . reference an external source is required to supply the reference to the ad7441/ad7451. this reference input can range from 100 mv to v dd . the specified reference is 2.5 v for the power supply range 2.7 v to 5.25 v. the reference input chosen for an appli- cation must never be greater than the power supply. errors in the reference source result in gain errors in the ad7441/ad7451 transfer function and add to the specified full-scale errors of the part. a capacitor of at least 0.1 f must be placed on the v ref pin. suitable reference sources for the ad7441/ad7451 include the ad780 and the adr421 . figure 27 shows a typical connec- tion diagram for the v ref pin. 1 ad780 nc 8 2 v in nc 7 3 gnd 6 4 temp 5 opsel trim v out ad7441/ ad7451* v ref 2.5v nc v dd nc v dd nc = no connect 10nf 0.1f 0.1f 0.1f *additional pins omitted for clarity. 0 3153-027 figure 27. typical v ref connection diagram for v dd = 5 v
ad7441/ad7451 rev. c | page 16 of 24 serial interface figure 2 and figure 3 show detailed timing diagrams for the serial interface of the ad7451 and the ad7441, respectively. the serial clock provides the conversion clock and also controls the transfer of data from the device during conversion. cs initiates the conversion process and frames the data transfer. the falling edge of cs puts the track-and-hold into hold mode and takes the bus out of three-state. the analog input is sampled and the conversion initiated at this point. the conversion requires 16 sclk cycles to complete. once 13 sclk falling edges have occurred, the track-and-hold goes back into track mode on the next sclk rising edge, as shown at point b in figure 2 and figure 3. on the 16th sclk falling edge, the sdata line goes back into three-state. if the rising edge of cs occurs before 16 sclks have elapsed, the conversion is terminated and the sdata line goes back into three-state. the conversion result from the ad7441/ad7451 is provided on the sdata output as a serial data stream. the bits are clocked out on the falling edge of the sclk input. the data stream of the ad7451 consists of four leading zeros followed by 12 bits of conversion data, provided msb first. the data stream of the ad7441 consists of four leading zeros, followed by the 10 bits of conversion data, followed by two trailing zeros, which is also provided msb first. in both cases, the output coding is straight (natural) binary. sixteen serial clock cycles are required to perform a conversion and to access data from the ad7441/ad7451. cs going low provides the first leading zero to be read in by the dsp or the microcontroller. the remaining data is then clocked out on the subsequent sclk falling edges, beginning with the second leading zero. thus, the first falling clock edge on the serial clock pro- vides the second leading zero. the final bit in the data transfer is valid on the 16th falling edge, having been clocked out on the previous (15th) falling edge. once the conversion is complete and the data has been accessed after the 16 clock cycles, it is important to ensure that, before the next conversion is initiated, enough time is left to meet the acquisition and quiet-time speci- fications (see the timing example 1 and timing example 2 sections). to achieve 1 msps with an 18 mhz clock, an 18-clock burst performs the conversion and leaves enough time before the next conversion for the acquisition and quiet time. in applications with slower sclks, it is possible to read in data on each sclk rising edge; that is, the first rising edge of sclk after the cs falling edge has the leading zero provided, and the 15th sclk edge has db0 provided.
ad7441/ad7451 rev. c | page 17 of 24 timing example 1 having f sclk = 18 mhz and a throughput rate of 1 msps gives a cycle time of 1/ throughput = 1/1,000,000 = 1 s a cycle consists of t 2 + 12.5 (1/ f sclk ) + t acquisition = 1 s therefore, if t 2 = 10 ns, then 10 ns + 12.5 (1/18 mhz) + t acquisition = 1 s t acquisition = 296 ns this 296 ns satisfies the requirement of 290 ns for t acquisition . from figure 28 , t acquisition comprises 2.5 (1/ f sclk ) + t 8 = t quiet where t 8 = 35 ns. this allows a value of 122 ns for t quiet , satisfying the minimum requirement of 60 ns. timing example 2 having f sclk = 5 mhz and a throughput rate of 315 ksps gives a cycle time of 1/ throughput = 1/315,000 = 3.174 s a cycle consists of t 2 + 12.5 (1/ f sclk ) + t acquisition = 3.174 s therefore, if t 2 is 10 ns, then 10 ns + 12.5 (1/5 mhz) + t acquisition = 3.174 s t acquisition = 664 ns this 664 ns satisfies the requirement of 290 ns for t acquisition . from figure 28 , t acquisition comprises 2.5 (1/f sclk ) + t 8 = t quiet where t 8 = 35 ns. this allows a value of 129 ns for t quiet , satisfying the minimum requirement of 60 ns. as in this example and with other slower clock values, the signal can already be acquired before the conversion is complete, but it is still necessary to leave 60 ns minimum t quiet between conver- sions. in example 2, the signal is fully acquired at approximately point c in figure 28 . t 2 t 8 t 6 t 5 t convert cs sclk 12345 13141516 12.5(1/ f sclk ) t acquisition 1/throughput t quiet 10ns b c 03153-028 figure 28. serial interface timing example
ad7441/ad7451 rev. c | page 18 of 24 modes of operation the operating mode of the ad7441/ad7451 is selected by controlling the logic state of the cs signal during a conversion. there are two operating modes: normal mode and power-down mode. the point at which cs is pulled high after the conversion is initiated determines whether the part enters power-down mode. similarly, if already in power-down, cs controls whether the device returns to normal operation or remains in power-down. these modes provide flexible power management options that can optimize the power dissipation/throughput rate ratio for differing application requirements. normal mode this mode is intended for fastest throughput rate performance. the user does not have to worry about any power-up times with the ad7441/ad7451 remaining fully powered up all the time. figure 29 shows the general diagram of the operation of the ad7441/ad7451 in this mode. the conversion is initiated on the falling edge of cs (see the serial interface section). to ensure that the part remains fully powered up, cs must remain low until at least 10 sclk falling edges elapse after the falling edge of cs . if cs is brought high any time after the 10th sclk falling edge, but before the 16th sclk falling edge, the part remains pow- ered up, however the conversion is terminated and sdata goes back into three-state. sixteen serial clock cycles are required to complete the conversion and access the complete conversion result. cs can idle high until the next conversion or can idle low until sometime prior to the next conversion. once a data transfer is completethat is, when sdata has returned to three-stateanother conversion can be initiated after the quiet time, t quiet , elapses again bringing cs low. 11 0 cs sclk s data 16 4 leading zeros + conversion result 0 3153-029 figure 29. normal mode operation power-down mode this mode is intended for use in applications where slower throughput rates are required; either the adc is powered down between each conversion or a series of conversions can be performed at a high throughput rate and the adc is then powered down for a relatively long duration between these bursts of conversions. when the ad7441/ad7451 are in power-down mode, all analog circuitry is powered down. for the ad7441/ad7451 to enter power-down mode, the conversion process must be interrupted by bringing cs high anywhere after the second falling edge of sclk and before the 10th falling edge of sclk, as shown in figure 30 . once cs has been brought high in this window of sclks, the part enters power-down, the conversion that was initiated by the falling edge of cs is terminated, and sdata goes back into three-state. the time from the rising edge of cs to sdata three-state enabled is never greater than t 8 (see the timing specifications section). if cs is brought high before the second sclk falling edge, the part remains in normal mode and does not power down. this avoids accidental power-down due to glitches on the cs line. to exit power-down mode and power up the ad7441/ad7451 again, a dummy conversion is performed. on the falling edge of cs , the device begins to power up and continues to do so as long as cs is held low until after the falling edge of the 10th sclk. the device is fully powered up after 1 s has elapsed and, as shown in figure 31 , valid data results from the next conversion. 1 10 sclk sdata three-state 2 cs 0 3153-030 figure 30. entering power-down mode
ad7441/ad7451 rev. c | page 19 of 24 cs sclk sdata 1 10 16 1 10 16 a this part is fully powered up with v in fully acquired part begins to power up invalid data valid data t power-up 03153-031 figure 31. exiting power-down mode if cs is brought high before the 10th falling edge of sclk, the ad7441/ad7451 again go back into power-down. this avoids accidental power-up due to glitches on the cs line or an inad- vertent burst of eight sclk cycles while cs is low. so although the device may begin to power up on the falling edge of cs , it again powers down on the rising edge of cs as long as it occurs before the 10th sclk falling edge. power-up time the power-up time of the ad7441/ad7451 is typically 1 s, which means that with any frequency of sclk up to 18 mhz, one dummy cycle is always sufficient to allow the device to power up. once the dummy cycle is complete, the adc is fully powered up and the input signal is acquired properly. the quiet time, t quiet , must still be allowedfrom the point at which the bus goes back into three-state after the dummy conversion to the next falling edge of cs . when running at the maximum throughput rate of 1 msps, the ad7441/ad7451 power up and acquire a signal within 0.5 lsb in one dummy cycle, that is, 1 s. when powering up from the power-down mode with a dummy cycle, as in figure 31 , the track-and-hold, which was in hold mode while the part was powered down, returns to track mode after the first sclk edge the part receives after the falling edge of cs . this is shown as point a in figure 31 . although at any sclk frequency one dummy cycle is sufficient to power up the device and acquire v in , it does not necessarily mean that a full dummy cycle of 16 sclks must always elapse to power up the device and acquire v in fully; 1 s is sufficient to power up the device and acquire the input signal. for example, when a 5 mhz sclk frequency is applied to the adc, the cycle time is 3.2 s (that is, 1/(5 mhz) 16). in one dummy cycle, 3.2 s, the part is powered up, and v in is acquired fully. however, after 1 s with a five mhz sclk, only five sclk cycles elapse. at this stage, the adc is fully powered up and the signal acquired. therefore, in this case, the cs can be brought high after the 10th sclk falling edge and brought low again after a time, t quiet , to initiate the conversion. when power supplies are first applied to the ad7441/ad7451, the adc can power up either in power-down mode or normal mode. for this reason, it is best to allow a dummy cycle to elapse to ensure that the part is fully powered up before attempting a valid conversion. likewise, if the user wants the part to power up in power-down mode, then the dummy cycle can be used to ensure the device is in power-down mode by executing a cycle such as that shown in figure 30 . once supplies are applied to the ad7441/ad7451, the power-up time is the same as that when powering up from power-down mode. it takes approxi- mately 1 s to power up fully in normal mode. it is not necessary to wait 1 s before executing a dummy cycle to ensure the desired mode of operation. instead, the dummy cycle can occur directly after power is supplied to the adc. if the first valid conversion is then performed directly after the dummy conversion, care must be taken to ensure that adequate acquisition time has been allowed. as mentioned earlier, when powering up from the power-down mode, the part returns to track mode upon the first sclk edge applied after the falling edge of cs . however, when the adc powers up initially after supplies are applied, the track-and- hold is already in track mode. this means (assuming one has the facility to monitor the adc supply current) that if the adc powers up in the desired mode of operation, a dummy cycle is not required to change mode. thus, a dummy cycle is also not required to place the track-and-hold into track.
ad7441/ad7451 rev. c | page 20 of 24 power vs. throughput rate by using the power-down mode on the device when not con- verting, the average power consumption of the adc decreases at lower throughput rates. figure 32 shows how, as the through- put rate is reduced, the device remains in its power-down state longer and the average power consumption reduces accordingly. for example, if the ad7441/ad7451 are operated in continuous sampling mode with a throughput rate of 100 ksps and an sclk of 18 mhz, and the device is placed in the power-down mode between conversions, then the power consumption during normal operation equals 9.25 mw maximum (for v dd = 5 v). if the power-up time is one dummy cycle (1 s) and the remain- ing conversion time is another cycle (1 s), then the ad7441/ ad7451 can be said to dissipate 9.25 mw for 2 s during each conversion cycle. (this power consumption figure assumes a very short time to enter power-down mode. this power figure increases as the burst of clocks used to enter power-down mode is increased). the ad7441/ad7451 consume just 5 w for the remaining 8 s. calculate the power numbers in figure 32 as follows: if the throughput rate = 100 ksps, then the cycle time = 10 s, and the average power dissipated during each cycle is (2/10) 9.25 mw = 1.85 mw for the same scenario, if v dd = 3 v, the power dissipation during normal operation is 4 mw maximum. the ad7441/ad7451 can now be said to dissipate 4 mw for 2 s during each conversion cycle. the average power dissipated during each cycle with a throughput rate of 100 ksps is, therefore, (2/10) 4 mw = 0.8 mw throughput (ksps) 100 03 5 0 power (mw) 0.01 50 100 150 200 250 300 0.1 1 10 v dd = 5v v dd = 3v 03153-032 figure 32. power vs. throughp ut rate for power-down mode for optimum power performance in throughput rates above 320 ksps, it is recommended that the serial clock frequency be reduced. microprocessor and dsp interfacing the serial interface on the ad7441/ad7451 allows the part to be connected directly to a range of different microprocessors. this section explains how to interface the ad7441/ad7451 with some of the more common microcontroller and dsp serial interface protocols. ad7441/ad7451 to adsp-21xx the adsp-21xx family of dsps is interfaced directly to the ad7441/ad7451 without any glue logic required. the sport control register is set up as follows: tfsw = rfsw = 1 alternate framing invrfs = invtfs = 1 active low frame signal dtype = 00 right justify data slen = 1111 16-bit data-words isclk = 1 internal serial clock tfsr = rfsr = 1 frame every word irfs = 0 itfs = 1 to implement power-down mode, slen is set to 1001 to issue an 8-bit sclk burst. the connection diagram is shown in figure 33 . adsp-21xx has the tfs and rfs of the sport tied together, with tfs set as an output and rfs set as an input. the dsp operates in alternate framing mode, and the sport control register is set up as described. the frame synchronization signal generated on the tfs is tied to cs , and, as with all signal processing applications, equidistant sampling is necessary. however, in this example, the timer interrupt is used to control the sampling rate of the adc, and, under certain conditions, equidistant sampling cannot be achieved. ad7441/ ad7451* adsp-21xx* sclk dr rfs tfs sclk sdata cs *additional pins removed for clarity. 0 3153-033 figure 33. interfacing to the adsp-21xx
ad7441/ad7451 rev. c | page 21 of 24 the timer registers, for example, are loaded with a value that provides an interrupt at the required sample interval. when an interrupt is received, a value is transmitted with tfs/dt (adc control word). the tfs is used to control the rfs and, there- fore, the reading of data. the frequency of the serial clock is set in the sclkdiv register. when the instruction to transmit with tfs is given, that is, ax0 = tx0, the state of the sclk is checked. the dsp waits until the sclk has gone high, low, and high before starting transmission. if the timer and sclk values are chosen such that the instruction to transmit occurs on or near the rising edge of sclk, then the data can either be transmitted or wait until the next clock edge. for example, the adsp-2111 has a master clock frequency of 16 mhz. if the sclkdiv register is loaded with the value of 3, an sclk of 2 mhz is obtained and eight master clock periods elapse for every one sclk period. if the timer registers are loaded with the value 803, 100.5 sclks occur between inter- rupts and subsequently between transmit instructions. this situation results in nonequidistant sampling, because the transmit instruction occurs on an sclk edge. if the number of sclks between interrupts is a whole integer figure of n, equidistant sampling is implemented by the dsp. ad7441/ad7451 to tms320c5x/c54x the serial interface on the tms320c5x/c54x uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices such as the ad7441/ad7451. the cs input allows easy interfacing between the tms320c5x/c54x and the ad7441/ad7451 without any glue logic required. the serial port of the tms320c5x/c54x is set up to operate in burst mode with internal clkx (tx serial clock) and fsx (tx frame sync). the serial port control register (spc) must have the following setup: fo = 0, fsm = 1, mcm = 1, and txm = 1. the format bit, fo, can be set to 1 to set the word length to eight bits in order to implement the power-down mode on the ad7441/ad7451. the connection diagram is shown in figure 34 . note that for signal processing applications, the frame synchronization signal from the tms320c5x/ c54x must provide equidistant sampling. ad7441/ ad7451* tms320c5x/ c54x* clkx dr fsx fsr sclk sdata cs clkr *additional pins removed for clarity. 03153-034 figure 34. interfacing to the tms320c5x/c54x ad7441/ad7451 to dsp56xxx the connection diagram in figure 35 shows how the ad7441/ ad7451 can be connected to the ssi (synchronous serial interface) of the dsp56xxx family of dsps from motorola. the ssi is operated in synchronous mode (syn bit in crb = 1) with internally generated 1-bit clock period frame sync for both tx and rx (bit fsl1 = 1 and bit fsl0 = 0 in crb). set the word length to 16 by setting bit wl1 = 1 and bit wl0 = 0 in cra. to implement the power-down mode on the ad7441/ad7451, the word length can be changed to eight bits by setting b it wl1 = 0 and bit wl0 = 0 in cra. note that for signal processing applica- tions, the frame synchronization signal from the dsp56xxx must provide equidistant sampling. ad7441/ ad7451* dsp56xxx* sclk srd sr2 sclk sdata cs *additional pins removed for clarity. 03153-035 figure 35. interfacing to the dsp56xxx
ad7441/ad7451 rev. c | page 22 of 24 grounding and layout hints the printed circuit board that houses the ad7441/ad7451 must be designed so that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be easily separated. a minimum etch technique is generally best for ground planes, as it gives the best shielding. digital and analog ground planes must be joined in only one place: a star ground point estab- lished as close to the gnd pin on the ad7441/ad7451 as possible. avoid running digital lines under the device, as this couples noise onto the die. the analog ground plane must be allowed to run under the ad7441/ad7451 to avoid noise coupling. the power supply lines to the ad7441/ad7451 must use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals like clocks must be shielded with digital grounds to avoid radiating noise to other sections of the board, and clock signals must never run near the analog inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board must run at right angles to each other. this reduces the effects of feedthrough on the board. a microstrip technique is by far the best but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. good decoupling is also important. all analog supplies must be decoupled with 10 f tantalum capacitors in parallel with 0.1 f capacitors to gnd. to achieve the best from these decoupling components, they must be placed as close as possible to the device. evaluating performance the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for con- trolling the board from a pc via the evaluation board controller. the evaluation board controller can be used in conjunction with the ad7441 and the ad7451 evaluation boards, as well as with many other analog devices, inc. evaluation boards ending with the cb designator, to demonstrate and evaluate the ac and dc performance of the ad7441 and the ad7451. the software allows the user to perform ac (fast fourier transform) and dc (histogram of codes) tests on the ad7441/ad7451. see the ad7441/ad7451 application note that accompanies the evaluation kit for more information.
ad7441/ad7451 rev. c | page 23 of 24 outline dimensions 13 56 2 8 4 7 2.90 bsc 1.60 bsc 1.95 bsc 0.65 bsc 0.38 0.22 0.15 max 1.30 1.15 0.90 seating plane 1.45 max 0.22 0.08 0.60 0.45 0.30 8 4 0 2.80 bsc pin 1 indicator compliant to jedec standards mo-178-ba figure 36. 8-lead small outline transistor package [sot-23] (rj-8) dimensions shown in millimeters compliant to jedec standards mo-187-aa 0.80 0.60 0.40 8 0 4 8 1 5 pin 1 0.65 bsc seating plane 0.38 0.22 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.08 3.20 3.00 2.80 5.15 4.90 4.65 0.15 0.00 0.95 0.85 0.75 figure 37. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters
ad7441/ad7451 rev. c | page 24 of 24 ordering guide model temperature range linearity error (lsb) 1 package description package option branding ad7451art-r2 ?40c to +85c 1.5 8-lead sot-23 rj-8 csa ad7451art-reel7 ?40c to +85c 1.5 8-lead sot-23 rj-8 csa ad7451artz-reel7 2 ?40c to +85c 1.5 8-lead sot-23 rj-8 c3t ad7451arm ?40c to +85c 1.5 8-lead msop rm-8 csa ad7451arm-reel7 ?40c to +85c 1.5 8-lead msop rm-8 csa ad7451armz 2 ?40c to +85c 1.5 8-lead msop rm-8 c3t AD7451BRT-R2 ?40c to +85c 1 8-lead sot-23 rj-8 c05 ad7451brt-reel7 ?40c to +85c 1 8-lead sot-23 rj-8 c05 ad7451brtz-reel7 2 ?40c to +85c 1 8-lead sot-23 rj-8 c3u ad7451brm ?40c to +85c 1 8-lead msop rm-8 c05 ad7451brm-reel7 ?40c to +85c 1 8-lead msop rm-8 c05 ad7451brmz 2 ?40c to +85c 1 8-lead msop rm-8 c3u ad7441brt-r2 ?40c to +85c 0.5 8-lead sot-23 rj-8 c0f ad7441brt-reel7 ?40c to +85c 0.5 8-lead sot-23 rj-8 c0f ad7441brtz-r2 2 ?40c to +85c 0.5 8-lead sot-23 rj-8 c4m ad7441brtz-reel7 2 ?40c to +85c 0.5 8-lead sot-23 rj-8 c4m ad7441brm ?40c to +85c 0.5 8-lead msop rm-8 c0f ad7441brm-reel7 ?40c to +85c 0.5 8-lead msop rm-8 c0f ad7441brmz 2 ?40c to +85c 0.5 8-lead msop rm-8 c4m eval-ad7451cb 3 evaluation board eval-ad7441cb 3 evaluation board eval-control brd2 4 controller board 1 linearity error here refers to integral nonlinearity error. 2 z = rohs compliant part. 3 this can be used as a standalone evaluation board or in conjunction with the evaluation board controller for evaluation/demons tration purposes. 4 the evaluation board controller is a complete unit allowing a pc to control and communicate with all analog devices evaluation boards ending in the cb designators. to order a complete evaluation kit, you must order the adc ev aluation board (eval-ad7451cb or eval-ad7441cb), the eval-control brd2, and a 12 v ac transformer. see the ad7451/ad7441 applicat ion note that accompanies the eval uation kit for more information. ?2003C2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. c03153-0- 3 /07(c)

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